K7P401822B sram equivalent, sram.
* 128Kx36 or 256Kx18 Organizations.
* 3.3V VDD, 2.5/3.3V VDDQ.
* LVTTL Input and Output Levels.
* Differential, PECL clock / Single ended or differential .
Pin Name K, K SAn DQn SS SW SWa SWb SWc SWd
M1, M2
Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Select Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Ena.
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