Core
* Max fCPU: 24 MHz
* Advanced STM8A core with Harvard architecture and 3-stage pipeline
* Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . ..

STM8AH5188

STM8AH5169

STM8AH5178

STM8AH5179

STM8AH5198

STM8AH5199

STM8AH519A

STM8AH51A8

STM8AH51A9

STM8AH51AA

STM8AH6169

STM8AH6176

STM8AH6178

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