Core
* Max fCPU: 24 MHz
* Advanced STM8A core with Harvard architecture and 3-stage pipeline
* Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . ..

STM8AF51A8

STM8AF51AA

STM8AF5168

STM8AF5169

STM8AF5178

STM8AF5179

STM8AF5188

STM8AF5189

STM8AF518A

STM8AF5198

STM8AF5199

STM8AF519A

STM8AF5268

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