Ultra-low power consumption technology VDD= 2.4 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execut.

(M; TA = 40 to +125C): 0.04167 s @ 24 MHz operation with high-speed on-chip oscillator or PLL clock Code flash memor.

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