R5F11CCC Datasheet | Renesas

RL78/I1E RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology VDD= 2.4 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator or PLL clock)Note to ultra-low speed (1 s: @ 1 MHz operation with highspeed on-chip oscillator or PLL clock) Multiply/divide/multiply & accumulate instructions are supported. Address space: 1 MB General-purpose registers: (8-bit register  8)  4 banks On-chip RAM: 8 KB Note For industrial applications (M; TA = - 40 to +125C): 0.04167 s @ 24 MHz operation with...