R5F11CBC - MCU

Renesas

Datasheet Details

Ultra-low power consumption technology VDD= 2.4 to 5.5 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.03125 s: @ 32 MHz operation with high-speed on-chip oscillator or PLL clock)Note to ultra-low speed (1 s: @ 1 MHz operation with highspeed on-chip oscillator or PLL clock) Multiply/divide/multiply & accumulate instructions are supported. Address space: 1 MB General-purpose registers:.

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Published: Aug 5, 2020 |