MK2049-45 pll equivalent, clock pll.
* Packaged in 20 pin SOIC
* 3.3 V + 5% operation
* Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase Transients,.
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a transl.
Image gallery
TAGS
Download (Size : 377.46KB)