Datasheet4U Logo Datasheet4U.com

IDT2305A - 3.3V ZERO DELAY CLOCK BUFFER

Description

The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

Features

  • Phase-Lock Loop Clock Distribution.
  • 10MHz to 133MHz operating frequency.
  • Distributes one clock input to one bank of five outputs.
  • Zero Input-Output Delay.
  • Output Skew < 250ps.
  • Low jitter.

📥 Download Datasheet

📁 Similar Datasheet

  • IDT2305A - 3.3V ZERO DELAY CLOCK BUFFER (IDT)
  • IDT2305 - 3.3V ZERO DELAY CLOCK BUFFER (IDT)
  • IDT2305B - 3.3V ZERO DELAY CLOCK BUFFER (IDT)
  • IDT2308 - 3.3V ZERO DELAY CLOCK MULTIPLIER (Integrated Device)
  • IDT2308A - 3.3V ZERO DELAY CLOCK MULTIPLIER (Integrated Device Technology)
  • IDT2308B - 3.3V ZERO DELAY CLOCK MULTIPLIER (IDT)
  • IDT2309 - 3.3V ZERO DELAY CLOCK BUFFER (Integrated Device)
  • IDT2309A - 3.3V ZERO DELAY CLOCK BUFFER (Integrated Device)
  • IDT2309NZ - NINE OUTPUT 3.3V CLOCK BUFFER (Integrated Device Technology)
  • IDT23S05 - 3.3V ZERO DELAY CLOCK BUFFER (Integrated Device)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
IDT2305A 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER IDT2305A FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2305A-1 for Standard Drive • IDT2305A-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Power down mode • Available in SOIC package FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The IDT2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.
Published: |