ICS93732 buffer equivalent, low cost ddr phase lock loop zero delay buffer.
* Low skew, low jitter PLL clock driver
* Max frequency supported = 266MHz (DDR 533)
* I2C for functional and output control
* Feedback pins for input to.
Features:
* Low skew, low jitter PLL clock driver
* Max frequency supported = 266MHz (DDR 533)
* I2C for functional and output control
* Feedback pins for input to output synchronization
* Spread Spectrum tolerant inputs
* 3.3.
Image gallery
TAGS
Download