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ICS93705 - DDR Phase Lock Loop Zero Delay Clock Buffer

Features

  • Low skew, low jitter PLL clock driver.
  • I2C for functional and output control.
  • Feedback pins for input to output synchronization.
  • Spread Spectrum tolerant inputs.
  • 3.3V tolerant CLK_INT input Switching Characteristics:.
  • PEAK - PEAK jitter (66MHz): 100MHz):.

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Datasheet Details

Part number ICS93705
Manufacturer Renesas
File Size 306.81 KB
Description DDR Phase Lock Loop Zero Delay Clock Buffer
Datasheet download datasheet ICS93705 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ICS9370 5 DDR Phase Lock Loop Zero Delay Clock Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.
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