ICS672-01 buffer equivalent, quadraclock quadrature delay buffer.
* Packaged in 16-pin SOIC
* Pb (lead) free package, RoHS compliant
* Input clock range from 5 MHz to 150 MHz (depends on
multiplier)
* Clock outputs from .
The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock (ICLK.
The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates .
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