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ICS663 - PLL BUILDING BLOCK

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Renesas

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ICS663 PLL BUILDING BLOCK by Renesas - Datasheet Preview — Datasheet preview – ICS663

Datasheet Details

Part number	ICS663
Manufacturer	Renesas
File Size	352.97 KB
Description	PLL BUILDING BLOCK
Datasheet	ICS663 Datasheet
Additional preview pages of the ICS663 datasheet.

Product details

Description

The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization.

Features

please refer to the ICS673-01. Features.
Packaged in 8-pin SOIC (Pb free).
Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V).
External PLL loop filter enables configuration for a wide range of input frequencies.
Ability to accept an input clock in the kHz range (video Hsync, for example).
25 mA output drive capability at TTL levels.
Lower power CMOS process.
+3.3 V ±5% or +5 V ±10% operating voltage.
Used.

📁 Similar Datasheet

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ICS650-05 - HDTV Clock Synthesizer (Integrated Circuit Systems)
ICS650-07B - Broadcom Clock Source (Integrated Circuit Systems)
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Other Datasheets by Renesas

ICS661 - PRECISION AUDIO CLOCK SOURCE
ICS662-03 - HDTV AUDIO/VIDEO CLOCK SOURCE
ICS664-02 - PECL DIGITAL VIDEO CLOCK SOURCE
ICS664-03 - DIGITAL VIDEO CLOCK SOURCE
ICS664-05 - DIGITAL VIDEO CLOCK SOURCE
ICS667-01 - HDTV CLOCK SYNTHESIZER

Published: Jun 4, 2020 |