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ICS663 Datasheet PLL BUILDING BLOCK

Manufacturer: Renesas

Overview: PLL BUILDING BLOCK DATASHEET ICS663.

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General Description

The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization.

Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer.

Through the use of external reference and VCO dividers (implemented with the ICS674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies.

Key Features

  • please refer to the ICS673-01. Features.
  • Packaged in 8-pin SOIC (Pb free).
  • Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V).
  • External PLL loop filter enables configuration for a wide range of input frequencies.
  • Ability to accept an input clock in the kHz range (video Hsync, for example).
  • 25 mA output drive capability at TTL levels.
  • Lower power CMOS process.
  • +3.3 V ±5% or +5 V ±10% operating voltage.
  • Used.

More Datasheets from Renesas

Part Number Description
ICS661 PRECISION AUDIO CLOCK SOURCE
ICS662-03 HDTV AUDIO/VIDEO CLOCK SOURCE
ICS664-01 DIGITAL VIDEO CLOCK SOURCE
ICS664-02 PECL DIGITAL VIDEO CLOCK SOURCE
ICS664-03 DIGITAL VIDEO CLOCK SOURCE
ICS664-05 DIGITAL VIDEO CLOCK SOURCE
ICS667-01 HDTV CLOCK SYNTHESIZER
ICS601-01 LOW PHASE NOISE CLOCK MULTIPLIER
ICS601-02 LOW PHASE NOISE CLOCK MULTIPLIER
ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER