ICS664-02 Datasheet PDF - Renesas PECL DIGITAL VIDEO CLOCK SOURCE Specs

ICS664-02 - PECL DIGITAL VIDEO CLOCK SOURCE

Datasheet Summary

Description

The ICS664-02 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment.

The ICS664-02 uses the latest Phase-Locked Loop (PLL) technology to provide excellent phase noise and long-term jitter performance for superior synchronization and S/N ratio.

Features

Packaged in 16-pin TSSOP.
Pb (lead) free package, RoHS compliant.
Clock or crystal input.
Low phase noise.
Low jitter.
Exact (0 ppm) multiplication ratios.
Power-down control.
Improved phase noise over ICS660.
Differential outputs.
Supports SMTE 292M HD-SDI standard for HDTV broadcast Block Diagram X2 X1/REFIN SELIN S3:0 4 VDD (P2) Crystal Oscillator GND (P6) VDD (P3) VDDO VDD (P10) PLL Clock Synthesi.

Datasheet Details

Part number	ICS664-02
Manufacturer	Renesas
File Size	327.47 KB
Description	PECL DIGITAL VIDEO CLOCK SOURCE
Datasheet	ICS664-02 Datasheet
Additional preview pages of the ICS664-02 datasheet.

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Full PDF Text Transcription

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PECL DIGITAL VIDEO CLOCK SOURCE DATASHEET ICS664-02 Description The ICS664-02 provides clock generation and conversion for clock rates commonly needed in HDTV digital video equipment. The ICS664-02 uses the latest Phase-Locked Loop (PLL) technology to provide excellent phase noise and long-term jitter performance for superior synchronization and S/N ratio. For audio sampling clocks generated from 27 MHz, use the ICS661. Please contact IDT if you have a requirement for an input and output frequency not included in this document. IDT can rapidly modify this product to meet special requirements.

Published: Jun 4, 2020 |