Datasheet4U Logo Datasheet4U.com

8S89832I - 1-to-4 Differential-to-LVDS Fanout Buffer

Datasheet Summary

Description

The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer.

The 8S89832I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel.

Features

  • Four differential LVDS output pairs.
  • IN, nIN input pairs can accept the following differential input levels: LVPECL, LVDS, SSTL.
  • 50 internal input termination to VT.
  • Maximum output frequency: 2GHz.
  • Output skew: 25ps (maximum).
  • Part-to-part skew: 200ps (maximum).
  • Propagation delay: 550ps (maximum).
  • Additive phase jitter, RMS: 0.09ps (typical).
  • Full 2.5V supply mode.
  • -40°C to 85°C ambient operating temperat.

📥 Download Datasheet

Datasheet preview – 8S89832I

Datasheet Details

Part number 8S89832I
Manufacturer Renesas
File Size 592.50 KB
Description 1-to-4 Differential-to-LVDS Fanout Buffer
Datasheet download datasheet 8S89832I Datasheet
Additional preview pages of the 8S89832I datasheet.

📁 Similar Datasheet

  • 8S89832I - 1-to-4 Differential-to-LVDS Fanout Buffer (IDT)
  • 8S89831I - Differential LVPECL-To-LVPECL/ECL Fanout Buffer (IDT)
  • 8S89833 - 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination (IDT)
  • 8S89834I - 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer (IDT)
Other Datasheets by Renesas
  • 8S89831I - Differential LVPECL-To-LVPECL/ECL Fanout Buffer
  • 8S89833 - 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
  • 8S89834I - 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer
  • 8S89296 - LVDS Programmable Delay Line

Full PDF Text Transcription

Click to expand full text
Low Skew, 1-to-4 Differential-to-LVDS Fanout Buffer 8S89832I Data Sheet Description The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer. The 8S89832I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin that may be useful for system test and debug purposes. The 8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
Published: |