524S buffer equivalent, low skew 1 to 4 clock buffer.
* Low additive phase jitter RMS: 50fs
* Extremely low skew outputs (50ps)
* Low cost clock buffer
* Packaged in 8-SOIC and 8-DFN, Pb-free
* ICLK is PD.
The 524S is a low skew, single input to four output, clock buffer. The 524S has best in class additive phase jitter of sub 50 fsec. The 524S is Power Down Tolerant (PDT). PDT designated inputs may be driven before VDD is applied, without damage to th.
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