HYS64T256022EDL-25F-B Datasheet, Qimonda AG

* Programmable self refresh rate via EMRS2 setting
* Programmable partial array refresh via EMRS2 settings
* Average Refresh Period 7.8 µs at a TCASE lower th.

The memory array is designed with stacked 1 Gbit DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The fi.

HYS64T256022EDL-2.5-B

HYS64T256022EDL-3-B

HYS64T256022EDL-3.7-B

HYS64T256022EDL-3S-B

HYS64T256020EDL-2.5-C

HYS64T256020EDL-25F-C

HYS64T256020EDL-3-C

HYS64T256020EDL-3.7-C

HYS64T256020EDL-3S-C

HYS64T128020

HYS64T128020EDL-2.5-C

HYS64T128020EDL-25F-C

HYS64T128020EDL-3-C