HYB18T512161B2F-25 Datasheet, Qimonda AG

The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
* Data masks (DM) for write data
* 1.8 V ± 0.1V VDD for [
  –20/
 .

The device is designed to comply with all DDR2 DRAM key features: 1. posted CAS with additive latency, 2. write latency.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS .

HYB18T512161B2F-20

HYB18T512161BF

HYB18T512160A

HYB18T512160AC-3.7

HYB18T512160AC-5

HYB18T512160AF

HYB18T512160AF-3.7

HYB18T512160AF-5

HYB18T512160B

HYB18T512160BC

HYB18T512160BF

HYB18T512400AC

HYB18T512400AC-3.7