HYB39S128407FE dram equivalent, 128-mbit synchronous dram.
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* Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Pow.
The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip archit.
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