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PCF8577 Datasheet Preview

PCF8577 Datasheet

LCD direct/duplex driver

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DEVELOPMENT DATA
This data sheet contains advance information and
specifications are subject to change without notice.
PCF8577
PCF8577A
LCD DIRECTIDUPLEX DRIVER WITH 12C-BUS INTERFACE
GENERAL DESCRIPTION
The PCF8577 is a single chip, silicon gate CMOS circuit. It is designed to drive liquid crystal displays
with up to 32 segments directly, or 64 segments in a duplex manner.
The two-line 12 Cbus interface substantially reduces wiring overheads in remote display applications.
Bus traffic is minimized in multiple IC applications by automatic address incrementing, hardware sub-
addressing and display memory switching (direct drive mode).
The PCF8577 and PCF8577 A differ only in their slave addresses.
Features
• Direct/duplex drive modes with up to 32/64 LCD-segment drive capabilitv per device
• Operating supply voltage: 2.5 to 9 V
• Low power consumption
• 12 C-bus interface
• Optimized pinning for single plane wiring
• Single-pin built-in oscillator
• Auto-incremented loading across device subaddress boundaries
• Display memory switching in direct drive mode
• May be used as 12 C-bus output expander
• System expansion up to 256 segments (512 segments with PCF8577 A)
• Power-on-reset blanks display
SCL
12 C BUS
SDA
39 r--
SEGMENT BYTE
INPUT
12C-BUS
REGISTERS
f-+-FI LTERS
CONTROLLER
AND
~40 MULTIPLEX
1+-+ -LOGIC
BACKPLANE
AND
SEGMENT
DRIVERS
t, I
II~~ tII
35 III t
T
PCF8577
CONTROL REGISTER
OSCILLATOR
I POOWNE-R-I
PCF8577A
AND
- AND
RESET
COMPARATOR
DIVIDER
38 1
6
1 S32
32 S1
33 BP1
34 A2/BP2
36 A1
37 AO/OSC
Fig.1 Block diagram.
7Z87556.3
PACKAGE OUTLINES
PCF8577P, PCF8577 AP: 40-lead 01 L; plastic (SOT129).
PCF8577T, PCF8577 AT: 40-lead mini-pack; plastic (VS040; SOT158A).
PCF8577T, PCF8577 AT: in blister tape.
PCF8577U/5, PCF8577 AU/5: wafer unsawn.
PCF8577U/10, PCF8577AU/10: chip-on-film frame carrier (FFC).
1(MarCh 1989
393




Philips

PCF8577 Datasheet Preview

PCF8577 Datasheet

LCD direct/duplex driver

No Preview Available !

PCF8577
PCF8577A
l
SDA
SCL
vss
AO/OSC
S27 6
S26 '7
A1
vDD
A2/BP2
BP1
S1
S23 S2
PCF8577
PCF8577A
S3
S21 S4
S20 S5
S19 S6
S18 15
S7
S17 25 S8
S16 S9
S15 S10
S14 S11
S13 20
S12
7Z87557.1
Fig.2 Pinning diagram.
PINNING
Supply
35 VOO
38 VSS
12 C-bus
4D SOA
39 SCL
positive supply
negative supply
12 C-bus data line
12 C-bus cI ock Iine
Inputs
36 A1
37 AD/OSC
hardware address line
hardware address line/oscillator pin
Outputs
1 - 32 S32 - S1 segment outputs
Input - Output
34 A2/BP2
33 BP1
harware address line/cascade sync
input/backplane output
cascade sync input/backplane output
FUNCTIONAL DESCRIPTION
Hardware subaddress AO, A 1, A2
The hardware subaddress lines AD, A 1, A2 are used to program the device subaddress for each PCF8577
on the bus. Lines AD and A2 are shared with OSC and BP2 respectively to reduce pin-out requirements.
AD/OSC Line AD is defined as LOW (logic D) when this pin is used for the local oscillator or when
connected to VSS. Line AD is defined as HIGH (logic 1) when connected to VOO.
A1 Line A1 must be defined as LOW (logic D) or as HIGH (logic 1) by connection to VSS or VOO
respectivel y.
A2/BP2
In the direct drive mode the second backplane signal BP2 is not used and the A2/BP2 pin is
exclusively the A2 input. Line A2 is defined as LOW (logic D) when connected to VSS or,
if this is not possible, by leaving it unconnected (internal pull-down). Line A2 is defined as
HIGH (logic 1) when connected to VOO.
In the duplex drive mode the second backplane signal BP2 is required and the A2 signal is
undefined. In this mode device selection is made exclusively from lines AD and A 1.
3M March 1989] (


Part Number PCF8577
Description LCD direct/duplex driver
Maker Philips
Total Page 16 Pages
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