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PLL602-35 Datasheet Preview

PLL602-35 Datasheet

(PLL602-35/37/38/39) Low Phase Noise Multiplier XO

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om PLL602-35/-37/-38/-39Preliminary
.c 750kHz – 800MHz Low Phase Noise Multiplier XO
U Universal Low Phase Noise IC’s
eet4FEATURES
ShSelectable 750kHz to 800MHz range.
taLow phase noise output (@ 10kHz frequency
aoffset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
.D106.25MHz, -125dBc/Hz for 155.52MHz, -
w110dBc/Hz for 622.08MHz).
wCMOS (PLL602-37), PECL (PLL602-35 and
w PLL602-38) or LVDS (PLL602-39) output.
12 to 25MHz crystal input.
mNo external load capacitor or varicap required.
oOutput Enable selector.
.cSelectable 1/16 to 32x frequency multiplier.
3.3V operation.
Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
t4UDESCRIPTIONS
The PLL602-35 (PECL with inverted OE), PLL602-37
e(CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS)
eare high performance and low phase noise XO IC
chips. They provide phase noise performance as low
has –125dBc at 1kHz offset (at 155MHz), by multiply-
ing the input crystal frequency up to 32x. They ac-
Scept fundamental parallel resonant mode crystals
tafrom 12 to 25MHz.
XOUT
SEL3^
SEL2^
OE
12 11 10
13
9
8
14 PLL602-3x 7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
aBLOCK DIAGRAM
.DSEL
wwOscillator
w mX+ Amplifier
t4U.coX-
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PLL602-3x
^: Internal pull-up
*: On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0
(pin 10), and pin 11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PLL602-38
0 (Default) Output enabled
1 Tri-state
PLL602-35
PLL602-37
PLL602-39
0 Tri-state
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL602-38
Logical states defined by CMOS levels for PLL602-35/-37/-39
www.DataShee47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 1




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PLL602-35 Datasheet Preview

PLL602-35 Datasheet

(PLL602-35/37/38/39) Low Phase Noise Multiplier XO

No Preview Available !

Preliminary PLL602-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
Selected Multiplier
00
1
1 Fin x 32
01
1
0 Fin / 8
01
1
1 Fin x 2
10
0
1 Fin / 2
10
1
0 Fin / 16
10
1
1 Fin x 4
11
11
0
0
0 Fin / 4
1 Fin x 8
11
1
0 Fin x 16
11
1
1 No multiplication
Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package
PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39)
Name
XIN
XOUT
OE
GND
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
VDD
TSSOP
Pin number
2
3
6
7,8,9,10,14
11
13
16
15
5
4
1, 12
3x3mm QFN
Pin number
12
13
16
1,2,3,4,8,11
5
7
Not available
9
15
14
6,10
Type
Description
I Crystal in connector.
I Crystal out connector.
I Output enable pin (see OE logic state table on page 1).
P GND.
O True output PECL
O Complementary output PECL.
I
I Multiplier selector pins. These pins have an internal pull-up
I that will default SEL to ‘1’ when not connected to GND.
I
P +3.3V VDD.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 2


Part Number PLL602-35
Description (PLL602-35/37/38/39) Low Phase Noise Multiplier XO
Maker PhaseLink
Total Page 9 Pages
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