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PLL602-12 Datasheet Preview

PLL602-12 Datasheet

Low Phase Noise LVDS XO

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om PLL602-12Preliminary
.c96MHz – 192MHz Low Phase Noise LVDS XO (12 – 24MHz Crystals)
eet4UFEATURES
ShLow phase noise output for the 96MHz to
ta192MHz range (-134 dBc at 10kHz offset).
aLVDS output.
.D12 to 24MHz crystal input.
wIntegrated crystal load capacitor: no external
wload capacitor required.
wOutput Enable selector.
m3.3V operation.
Available in 16 Pin TSSOP or SOIC.
.coDESCRIPTION
The PLL602-12 is a monolithic low jitter and low
Uphase noise (-134dBc/Hz @ 10kHz offset) XO IC
t4with LVDS output, for 96MHz to 192MHz output
range. It provides a low phase noise reference
frequency using a low cost crystal.
eThe chip delivers an output frequency of FXIN x 8.
eThis makes the PLL602-12 ideal for a wide range of
applications, including 155.52MHz for SONET.
hBLOCK DIAGRAM
PIN CONFIGURATION
VDD
VDD
XIN
XOUT
OE
N/C
GND
GND
1
2
3
4
5
6
7
8
16 VDD
15 GND_BUF
14 CLKBAR
13 VDD_BUF
12 CLK
11 GND_BUF
10 GND
9 GND
FOUT = FXIN x 8
OE (Pin 5)
0
1 (Default)
Output State
Tri-state
Output enabled
ataSReference
.DDivider
XIN
XOUT
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLKBAR
CLK
www www.DataSheet4U.com47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 1




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PLL602-12 Datasheet Preview

PLL602-12 Datasheet

Low Phase Noise LVDS XO

No Preview Available !

Preliminary PLL602-12
96MHz – 192MHz Low Phase Noise LVDS XO (12 – 24MHz Crystals)
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
N/C
GND
GND_BUF
CLK
VDD_BUF
CLKB
Number
1,2,16
3
4
5
6
7,8,9,10
11,15
12
13
14
Type
Description
P +3.3V Power supply connectors.
I Crystal input pin.
I Crystal output pin.
I
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
- Not connected.
P GND Power connectors.
P GND connector for output buffers.
O True clock output pin.
P +3.3V Power supply connector for output buffers.
O Complementary clock output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
VDD 7 V
VI
VSS-0.5 VDD+0.5
V
VO VSS-0.5 VDD+0.5 V
TS -65 150 °C
TA 0 70 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 2


Part Number PLL602-12
Description Low Phase Noise LVDS XO
Maker PhaseLink
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PLL602-12 Datasheet PDF





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