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PYA28C64 Datasheet Preview

PYA28C64 Datasheet

EEPROM

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FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Fast Byte Write (200µs or 1 ms)
Low Power CMOS:
- 60 mA Active Current
- 150 µA Standby Current
Fast Write Cycle Time
RDY/BUSY pin is not connected for the
PYA28C64X
PYA28C64(X)
8K X 8 EEPROM
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTION
The PYA28C64 is a 5 Volt 8Kx8 EEPROM. The PYA28C64
features DATA and RDY/BUSY (PYA28C64 only) to indicate
early completion of a Write Cycle. Data Retention is 10
Years. The device is available in a 28-Pin 600 mil wide
Ceramic DIP and 32-Pin LCC.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (C5-1)
Document # EEPROM105 REV B
LCC (L6)
NOTE: The RDY/BUSY pin is not connected for the PYA28C64X.
Revised June 2012




PYRAMID

PYA28C64 Datasheet Preview

PYA28C64 Datasheet

EEPROM

No Preview Available !

PYA28C64 - 8K x 8 EEPROM
OPERATION
READ
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
BYTE WRITE
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28C64 supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically con-
tinue to completion.
CHIP CLEAR
The contents of the entire memory of the PYA28C64 may
be set to the high state by the CHIP CLEAR operation.
By setting CE low and OE to 12 volts, the chip is cleared
when a 10 msec low pulse is applied to WE.
DEVICE IDENTIFICATION
An extra 32 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12 ±
0.5V and using address locations 1FE0H to 1FFFH the
additional bytes may be written to or read from in the
same manner as the regular memory array.
DATA POLLING
The PYA28C64 features DATA Polling as a method to in-
dicate to the host system that the byte write cycle has
completed. DATA Polling allows a simple bit test opera-
tion to determine the status of the PYA28C64, eliminat-
ing additional interrupts or external hardware. During the
internal programming cycle, any attempt to read the last
byte written will produce the complement of that data on
I/O7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx).
Once the programming cycle is complete, I/O7 will reflect
true data.
READY/BUSY
Pin 1 is an open drain RDY/BUSY output that can be
used to detect the end of a write cycle. RDY/BUSY is
actively pulled low during the write cycle and is released
at the completion of the write. The open drain connec-
tion allows for OR-tying of several devices to the same
RDY/BUSY line. The RDY/BUSY pin is not connected
for the PYA28C64X.
MAXIMUM RATINGS(1)
Sym Parameter
VCC
VTERM
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
6.25V)
TA Operating Temperature
TBIAS Temperature Under Bias
TSTG Storage Temperature
PT Power Dissipation
IOUT DC Output Current
Value
-0.3 to +6.25
-0.5 to +6.25
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMENDED OPERATING CONDITIONS
Grade(2)
Military
Ambient Temp GND
-55°C to +125°C 0V
VCC
5.0V ± 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Sym Parameter
Conditions Typ Unit
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 0V
10 pF
VOUT = 0V 10 pF
Document # EEPROM105 REV B
Page 2


Part Number PYA28C64
Description EEPROM
Maker PYRAMID
Total Page 10 Pages
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