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PYRAMID

PYA28HC256 Datasheet Preview

PYA28HC256 Datasheet

STATIC CMOS RAM

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FEATURES
Access Times of 70, 90 and 120ns
Single 5V±10% Power Supply
Simple Byte and Page Write
Low Power CMOS:
- 80 mA Active Current
- 3 mA Standby Current
Fast Write Cycle Times
PYA28HC256
HIGH SPEED 32K x 8 EEPROM
Software Data Protection
CMOS & TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Data Retention: 10 Years
Available in the following package:
– 28-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
DESCRIPTION
The PYA28HC256 is a 5 Volt 32Kx8 EEPROM. The device
supports 64-byte page write operation. The PYA28HC256
features DATA and Toggle Bit Polling as well as a system
software scheme used to indicate early completion of a
Write Cycle. The device also includes user-optional soft-
ware data protection. Data Retention is 10 Years. The
device is available in a 28-Pin 600 mil wide Ceramic DIP
and 32-Pin LCC.
Functional Block Diagram
Pin Configuration
Document # EEPROM106 REV 03
DIP (C5-1)
LCC (L6)
Revised October 2014




PYRAMID

PYA28HC256 Datasheet Preview

PYA28HC256 Datasheet

STATIC CMOS RAM

No Preview Available !

OPERATION
READ
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
BYTE WRITE
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28HC256 supports both
a CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, which-
ever occurs last. Similarly, the data is latched internally
by the rising edge of either CE or WE, whichever occurs
first. A byte write operation, once initiated, will automati-
cally continue to completion.
PAGE WRITE
The page write feature of the PYA28HC256 allows 1
to 64 bytes of data to be consecutively written to the
PYA28HC256 during a single internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A6 through A14) for each
subsequent valid write cycle to the part during this opera-
tion must be the same as the initial page address. The
bytes within the page to be written are specified with the
A0 through A5 inputs.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional 1 to 63 bytes in the same man-
ner as the first byte was written. Each successive byte
load cycle, started by the WE HIGH to LOW transition,
must begin within 150µs of the falling edge of the pre-
ceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 150µs, the internal automatic pro-
gramming cycle will commence. There is no page write
window limitation. Effectively, the page write window is
Document # EEPROM106 REV 03
PYA28HC256 - HIGH SPEED 32K x 8 EEPROM
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 150µs.
WRITE STATUS BITS
The PYA28HC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus
as shown below.
DATA POLLING
The PYA28HC256 features DATA Polling as a meth-
od to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
PYA28HC256, eliminating additional interrupts or external
hardware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the comple-
ment of that data on I/O7 (i.e., write data=0xxx xxxx, read
data=1xxx xxxx). Once the programming cycle is com-
plete, I/O7 will reflect true data. Note: If the PYA28HC256
is in the protected state and an illegal write operation is
attempted, DATA Polling will not operate.
TOGGLE BIT
The PYA28HC256 also provides another method for de-
termining when the internal write cycle is complete. Dur-
ing the internal programming cycle, I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent attempts
to read the device. When the internal cycle is complete
the toggling will cease and the device will be accessible
for addtional read or write operations.
DATA PROTECTION
Pyramid has incorporated both hardware and software
features that will protect the memory against inadvertent
writes during transitions of the host system power sup-
ply.
Hardware Protection
Hardware features protect against inadvertent writes to
the PYA28C256 in the following ways: (a) VCC sense - if
VCC is below 3.8V (typical) the write function is inhibited;
(b) VCC power-on delay - once VCC has reached 3.8V
the device will automatically time out 5 ms (typical) before
allowing a write; (c) write inhibit - holding any one of OE
low, CE high or WE high inhibits write cycles; and (d)
noise filter - pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a write cycle.
Software Data Protection
A software controlled data protection feature has been
implemented on the PYA28C256. When enabled, the
software data protection (SDP), will prevent inadvertent
writes. The SDP feature may be enabled or disabled by
the user; the PYA28C256 is shipped from Pyramid with
SDP disabled.
SDP is enabled by the host system issuing a series of
Page 2


Part Number PYA28HC256
Description STATIC CMOS RAM
Maker PYRAMID
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