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  ON Semiconductor Electronic Components Datasheet  

NB7L585R Datasheet

2.5V/3.3V 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer

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NB7L585R
2.5V/3.3V, 7GHz/10Gbps
Differential 2:1 Mux Input to
1:6 RSECL Clock/Data
Fanout Buffer / Translator
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L585R is a differential 1:6 RSECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585R produces six identical output copies of Clock or
Data operating up to 7 GHz or 10 Gb/s, respectively. As such,
NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock/Data distribution applications.
The NB7L585R is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585R is a member of the GigaCommfamily of high
performance clock products.
Features
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz Typical
www.DataSRheaent4dUom.coCmlock Jitter < 0.8 ps RMS
Low Skew 1:6 RSECL Outputs, 20 ps max
2:1 MultiLevel Mux Inputs
160 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Differential RSECL Outputs, 400 mV peaktopeak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm
40ºC to +85ºC Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
585R
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
+
SEL
VREFAC0
IN0
VT0
50 W
50 W
IN0
0
Q0
Q0
Q1
Q1
Q2
IN1
VT1
50 W
50 W
IN1
VREFAC1
VCC
GND
1
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2009
October, 2009 Rev. 0
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1 Publication Order Number:
NB7L585R/D


  ON Semiconductor Electronic Components Datasheet  

NB7L585R Datasheet

2.5V/3.3V 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer

No Preview Available !

NB7L585R
Exposed
Pad (EP)
32 31 30 29 28 27 26 25
IN0 1
VT0 2
VREFAC0 3
IN0 4
IN1 5
VT1 6
VREFAC1 7
IN1 8
24 GND
23 VCC
NB7L585R
22 Q2
21 Q2
20 Q3
19 Q3
18 VCC
17 GND
9 10 11 12 13 14 15 16
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
CLK Input Selected
0 IN0
1 IN1
*Defaults HIGH when left open.
Figure 2. Pinout: QFN32 (Top View)
Table 2. PIN DESCRIPTION
Pin Number Pin Name
I/O
Pin Description
1,4 IN0, IN0 LVPECL, CML, Noninverted, Inverted, Differential Data Inputs internally biased to VCC/2
5,8
IN1, IN1
LVDS Input
2,6 VT0, VT1
Internal 100 W Centertapped Termination Pin for IN0 / IN0 and IN1 / IN1
31 SEL LVTTL/LVCMOS Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left
Input
open
10 NC
No Connect
11, 16, 18
23, 25, 30
VCC
PfoorsciotivrreecStuDpCplyanVdolAtaCgeo.pAelrlaVtiCoCn.pins must be connected to the positive power supply
29, 28
27, 26
22, 21
20, 19
www.DataShe11e53t4,, U1142.com
Q0, Q0
Q1, Q1
Q2,Q2
Q3, Q3
Q4, Q4
Q5, Q5
RSECL Output Noninverted, Inverted Differential Outputs Note 1.
9, 17, 24, 32
GND
Negative Supply Voltage, connected to Ground
3 VREFAC0 Output Voltage Reference for CapacitorCoupled Inputs
7 VREFAC1
EP
The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heatsinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7L585R
Description 2.5V/3.3V 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer
Maker On Semiconductor
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