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NB7L72M Datasheet

Multi-Level Inputs w/ Internal Termination

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NB7L72M
2.5V / 3.3V Differential 2 x 2
Crosspoint Switch with
CML Outputs Clock/Data
Buffer/Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB7L72M is a high bandwidth, low voltage, fully differential
2 x 2 crosspoint switch with CML outputs. The NB7L72M design is
optimized for low skew and minimal jitter as it produces two identical
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, the NB7L72M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
The differential IN/IN inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels (see
Figure 11). The 16 mA differential CML outputs provide matching
internal 50 W terminations and produce 400 mV output swings when
externally terminated with a 50 W resistor to VCC (see Figure 9).
The NB7L72M is the 2.5 V/3.3 V version of the and NB7V72M and
is offered in a low profile 3x3 mm 16pin QFN package. Application
notes, models, and support documentation are available at
www.onsemi.com.
The NB7L72M is a member of the GigaCommfamily of high
performance clock products.
Features
Maximum Input Data Rate > 10 Gb/s
Data Dependent Jitter < 10 ps pkpk
www.DataSMheaext4iUm.cuommInput Clock Frequency > 7 GHz
Random Clock Jitter < 0.5 ps RMS, Max
150 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV peaktopeak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3mm x 3mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
72M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
+
SEL0
IN0
VT0
IN0
0 Q0
1 Q0
IN1 0
VT1
IN1 +
SEL1
1
Figure 1. Logic Diagram
Q1
Q1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
September, 2008 Rev. 1
1
Publication Order Number:
NB7L72M/D


  ON Semiconductor Electronic Components Datasheet  

NB7L72M Datasheet

Multi-Level Inputs w/ Internal Termination

No Preview Available !

NB7L72M
VT0 SEL0 GND VCC Exposed Pad (EP)
16 15 14 13
IN0 1
IN0 2
IN1 3
IN1 4
NB7L72M
12 Q0
11 Q0
10 Q1
9 Q1
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0*
SEL1*
Q0
Q1
L L IN0 IN0
L H IN0 IN1
H L IN1 IN0
H H IN1 IN1
*Defaults HIGH when left open
5678
VT1 SEL1 GND VCC
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 IN0 LVPECL, CML, Noninverted Differential Input. (Note 1)
LVDS Input
2 IN0 LVPECL, CML, Inverted Differential Input. (Note 1)
LVDS Input
3 IN1 LVPECL, CML, Inverted Differential Input. (Note 1)
LVDS Input
4 IN1 LVPECL, CML, Noninverted Differential Input. (Note 1)
LVDS Input
5 VT1
Internal 50 W Termination Pin for IN1 and IN1.
6 SEL1 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
7 GND
Negative Supply Voltage
8 VCC
Positive Supply Voltage
9 Q1
CML Output
Noninverted Differential Output. (Note 1)
10 Q1
www.DataSheet4U.com
11 Q0
CML Output
CML Output
Inverted Differential Output. (Note 1)
Inverted Differential Output. (Note 1)
12 Q0
CML Output
Noninverted Differential Output. (Note 1)
13 VCC
Positive Supply Voltage
14 GND
Negative Supply Voltage
15 SEL0
LVCMOS Input
Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
16 VT0
EP
Internal 50 W Termination Pin for IN0 and IN0
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to the die, and is recommended to be electrically and
thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7L72M
Description Multi-Level Inputs w/ Internal Termination
Maker ON Semiconductor
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