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NB7L585 Datasheet

2.5 V / 3.3 V Differential 2:1 Mux Input To 1:6 LVPECL Clock/Data Fanout Buffer / Translator

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NB7L585
2.5V / 3.3V Differential 2:1
Mux Input to 1:6 LVPECL
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585 produces six identical output copies of Clock or Data
operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The NB7L585 is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32−pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585 is a member of the GigaCommfamily of high
performance clock products.
Features
Maximum Input Data Rate > 8 Gb/s
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 5 GHz
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:6 LVPECL Outputs, 20 ps max
2:1 Multi−Level Mux Inputs
175 ps Typical Propagation Delay
55 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peak−to−peak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN−32 Package, 5mm x 5mm
−40ºC to +85ºC Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
585
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
+
SEL
VREFAC0
IN0
50 W
VT0
50 W
IN0
0
Q0
Q0
Q1
Q1
Q2
IN1
50 W
VT1
50 W
IN1
VREFAC1
VCC
GND
1
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
1 Publication Order Number:
NB7L585/D


  ON Semiconductor Electronic Components Datasheet  

NB7L585 Datasheet

2.5 V / 3.3 V Differential 2:1 Mux Input To 1:6 LVPECL Clock/Data Fanout Buffer / Translator

No Preview Available !

NB7L585
Exposed
Pad (EP)
32 31 30 29 28 27 26 25
IN0 1
VT0 2
VREFAC0 3
IN0 4
IN1 5
VT1 6
VREFAC1 7
IN1 8
24 GND
23 VCC
NB7L585
22 Q2
21 Q2
20 Q3
19 Q3
18 VCC
17 GND
9 10 11 12 13 14 15 16
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
CLK Input Selected
0 IN0
1 IN1
*Defaults HIGH when left open.
Figure 2. Pinout: QFN−32 (Top View)
Table 2. PIN DESCRIPTION
Pin Number Pin Name
I/O
Pin Description
1,4 IN0, IN0 LVPECL, CML, Non−inverted, Inverted, Differential Data Inputs internally biased to VCC/2
5,8
IN1, IN1
LVDS Input
2,6 VT0, VT1
Internal 100 W Center−tapped Termination Pin for IN0 / IN0 and IN1 / IN1
31 SEL LVTTL/LVCMOS Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left
Input
open
10 NC
− No Connect
11, 16, 18
23, 25, 30
VCC
− Positive Supply Voltage. All VCC pins must be connected to the positive power supply
for correct DC and AC operation.
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
Q0, Q0
Q1, Q1
Q2,Q2
Q3, Q3
Q4, Q4
Q5, Q5
LVPECL Output Non−inverted, Inverted Differential Outputs Note 1.
9, 17, 24, 32
GND
Negative Supply Voltage, connected to Ground
3 VREFAC0 − Output Voltage Reference for Capacitor−Coupled Inputs
7 VREFAC1
− EP
− The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then the device will be susceptible to self−oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7L585
Description 2.5 V / 3.3 V Differential 2:1 Mux Input To 1:6 LVPECL Clock/Data Fanout Buffer / Translator
Maker ON Semiconductor
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NB7L585 Datasheet PDF






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