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NB7L572 - 2.5 V / 3.3 V Differential 4:1 Mux Input To 1:2 LVPECL Clock/Data Fanout/Translator

General Description

Pin Name I/O Description 1, 4 5, 8 25, 28 29, 32 IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 LVPECL, CML, Non

inverted, Inverted, Differential Clock or Data Inputs.

tapped Termination Pin for INx / INx 15 18 14, 19 SE

Key Features

  • Input Data Rate > 10.7 Gb/s Typical.
  • Data Dependent Jitter < 15 ps.
  • Maximum Input Clock Frequency > 7 GHz Typical.
  • Random Clock Jitter < 0.8 ps RMS.
  • Low Skew 1:2 LVPECL Outputs, < 15 ps max.
  • 4:1 Multi.
  • Level Mux Inputs, Accepts LVPECL, CML LVDS.
  • 150 ps Typical Propagation Delay.
  • 45 ps Typical Rise and Fall Times.
  • Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical.
  • Operating Range: VCC = 2.375.

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Datasheet Details

Part number NB7L572
Manufacturer onsemi
File Size 134.32 KB
Description 2.5 V / 3.3 V Differential 4:1 Mux Input To 1:2 LVPECL Clock/Data Fanout/Translator
Datasheet download datasheet NB7L572 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NB7L572 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator Multi−Level Inputs w/ Internal Termination The NB7L572 is a high performance differential 4:1 Clock/Data input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The INx/INx inputs includes internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The NB7L572 incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical LVPECL output copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The NB7L572 INx/INx inputs, outputs and core logic are powered by a 2.