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NB6L14S - 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator

Description

Pin Name I/O Description 1 Q1 LVDS Output Non

inverted IN output.

Typically loaded with 100 W receiver termination resistor across differential pair.

Inverted IN output.

Features

  • Maximum Input Clock Frequency > 2.0 GHz.
  • Maximum Input Data Rate > 2.5 Gb/s.
  • 1 ps Maximum of RMS Clock Jitter.
  • Typically 10 ps of Data Dependent Jitter.
  • 380 ps Typical Propagation Delay.
  • 120 ps Typical Rise and Fall Times.
  • Single Power Supply; VCC = 2.5 $ 5%.
  • VREF_AC Reference Output.
  • These are Pb.
  • Free Devices Device DDJ = 10 ps http://onsemi. com 1 QFN.
  • 16 MN SUFFIX CASE 485G.

📥 Download Datasheet

Datasheet Details

Part number NB6L14S
Manufacturer onsemi
File Size 224.77 KB
Description 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
Datasheet download datasheet NB6L14S Datasheet

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Part Number Description
NB6L14 Differential 1:4 LVPECL Fanout Buffer
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NB6L14S 2.5 V 1:4 AnyLevel] Differential Input to LVDS Fanout Buffer/Translator The NB6L14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML, LVDS, or HSCL. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6L14S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6L14S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels.
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