P50N03LDG - N-Channel Logic Level Enhancement Mode Field Effect Transistor

NIKO-SEM

Download the P50N03LDG datasheet PDF. This datasheet also covers the P50N03LDG-Niko variant, as both devices belong to the same n-channel logic level enhancement mode field effect transistor family and are provided as variant models within a single manufacturer datasheet.

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P50N03LDG n-channel logic level enhancement mode field effect transistor by NIKO-SEM - Datasheet Preview — Note: The manufacturer provides a single datasheet file (P50N03LDG-Niko-Sem.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	P50N03LDG
Manufacturer	NIKO-SEM
File Size	304.73 KB
Description	N-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet	P50N03LDG Datasheet

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Other Datasheets by NIKO-SEM

Part Number	Description
P50N03LD	N-Channel MOSFET
P50N03LSG	N-Channel Logic Level Enhancement Mode Field Effect Transistor
P50N02LD	N-Channel MOSFET
P50N02LS	N-Channel MOSFET
P5003QVG	N&P-Channel MOSFET

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P50N03LDG TO-252 (DPAK) Lead-Free D PRODUCT SUMMARY V(BR)DSS 27 RDS(ON) 12m ID 50A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Avalanche Current Avalanche Energy Repetitive Avalanche Energy Power Dissipation 2 1 SYMBOL VGS LIMITS ±20 50 35 150 33 250 8.6 50 30 -55 to 150 275 UNITS V TC = 25 °C TC = 100 °C ID IDM IAR A L = 0.1mH L = 0.05mH TC = 25 °C TC = 100 °C EAS EAR PD Tj, Tstg TL mJ W Operating Junction & Storage Temperature Range Lead Temperature ( /16” from case for 10 sec.