CGS701ATV Datasheet | National Semiconductor

CGS701AV mercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver December 1995 CGS701AV mercial Low Skew PLL 1 to 8 CMOS Clock Driver CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General Description CGS701A is an off the shelf clock driver specifically designed for today’s high speed designs It provides low skew outputs which are produced at different frequencies from three fixed input references The XTALIN input pin is designed to be driven from a 25 MHz- 40 MHz crystal oscillator The PLL using a charge pump and an internal loop filter multiplies this input frequency to create a maximum output frequency of four times the input The device includes a TRI-STATE control pin to disable the outputs This feature allows for low frequency functional testing and debugging Also included is an EXTSEL pin to allow testing the chip via an external source The EXTSEL pin once set to high causes the External-Clock MUX to change its input from the output of the VCO and Counter to the external clock signal provided via SKWTST input pin (continued) Features Y Y Y Y Y Y Y Y Y Y Y Y Y Y Guaranteed 400 ps pin-to-pin skew (t OSHL and t OSLH) on 1X outputs Pentium and Power PCTM patible g 300 ps propagation delay Output buffer of eight drivers for large fanout 25 MHz - 160 MHz output frequency range Outputs operating at 4X 2X 1X of the reference frequency for multifrequency bus applications Selectable output frequency Internal loop filter to reduce noise and jitter Separate analog and digital VCC and ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output current drive a 30 b30 m A IOL IOH Industrial temperature of b40 C to a 85 C 28-pin PLCC for optimum skew performance Guaranteed 2k volts ESD protection Connection Diagram Pin Assignment for PLCC Pin Description PLCC Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27...