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CGS701V - Low Skew PLL 1 to 8 CMOS Clock Driver

Description

CGS701 is an off the shelf clock driver specifically designed for today's high speed designs.

It provides low skew outputs which are produced at different frequencies from three fixed input references.

The XTALIN input pin is designed to be driven from a 15 MHz-50 MHz crystal oscillator.

Features

  • Guaranteed and tested: 500 ps pin-to-pin skew (tOSHL and tOSLH) on 1X out- puts. ± 500 ps propagation delay.
  • Output buffer of eight drivers for large fanout.
  • 25 MHz-160 MHz output frequency range.
  • Outputs operating at 4X, 2X, 1X of the reference frequency for multifrequency bus.

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Datasheet preview – CGS701V

Datasheet Details

Part number CGS701V
Manufacturer National Semiconductor
File Size 178.40 KB
Description Low Skew PLL 1 to 8 CMOS Clock Driver
Datasheet download datasheet CGS701V Datasheet
Additional preview pages of the CGS701V datasheet.

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Full PDF Text Transcription

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,.. o ~ o ~DNaStemiicoonnduactlor PRELIMINARY CGS701V Commercial/CGS701TV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver General Description CGS701 is an off the shelf clock driver specifically designed for today's high speed designs. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from a 15 MHz-50 MHz crystal oscillator. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATE® control pin to disable the outputs. This feature allows for low frequency functional testing and debugging.
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