NT5CC128M8DN sdram equivalent, 1gb ddr3 sdram.
and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential c.
* The timing specification of high speed bin is backward compatible with low speed bin
* 8 Internal memory banks.
The 1Gb Double-Data-Rate-3 (DDR3/L) B-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank de.
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