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PTN3332 Datasheet

High speed differential line receiver

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PTN3332
High speed differential line receiver
Rev. 01 — 07 January 2004
Product data
1. Description
The PTN3332 is a differential line receiver that implements the electrical
characteristics of Low-Voltage Differential Signaling (LVDS). This device meets or
exceeds the requirements of the ANSI TIA/EIA-644 Standard. LVDS is used to
achieve higher data rates on commonly used media. LVDS overcomes the limitations
of achievable slew rates and EMI restrictions of previous differential signaling
techniques. The PTN3332 operates at a 3.3 volt supply level. Any of the four
differential receivers provides a valid logical output state with a ±100 mV differential
input voltage within the input common-mode voltage range. The input common-mode
voltage range allows 1 volt of ground potential difference between two LVDS nodes.
The intended application of this device is for point-to-point baseband transmission
rates over a controlled impedance media of approximately 100 . The maximum
rates and distance of data transfer are dependent upon the attenuation
characteristics of the media selected and the noise coupling to the environment.
The PTN3332 is designed to function over the full industrial temperature range of
40 °C to +85 °C.
2. Features
s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard
s Designed for signaling rates of up to 400 Mbps
s Differential input thresholds of ±100 mV
s Power dissipation of 60 mW typical at 200 MHz
s Typical propagation delay of 2.6 ns
s Low Voltage TTL (LVTTL) logic output levels
s Pin compatible with AM26LS32 and SN65LVDS32
s Open-circuit fail safe.
3. Applications
s Low voltage, low EMI, high speed differential signal receiver
s Point-to-point high speed data transmission
s High performance switches and routers.


NXP Semiconductors Electronic Components Datasheet

PTN3332 Datasheet

High speed differential line receiver

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Philips Semiconductors
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4. Pinning information
4.1 Pinning
PTN3332
High speed differential line receiver
1B 1
1A 2
1Y 3
G4
2Y 5
2A 6
2B 7
GND 8
16 VCC
15 4B
14 4A
13 4Y
12 G
11 3Y
10 3A
9 3B
002aaa026
Fig 1. TSSOP16 pin configuration.
1B 1
1A 2
1Y 3
G4
2Y 5
2A 6
2B 7
GND 8
16 VCC
15 4B
14 4A
13 4Y
12 G
11 3Y
10 3A
9 3B
002aaa027
Fig 2. SO16 pin configuration.
4.2 Pin description
Table 1:
Symbol
1B
1A
1Y
G
2Y
2A
2B
GND
3B
3A
3Y
G
4Y
4A
4B
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
LVDS inverting input
LVDS non-inverting input
LVTTL output
Enable (active-HIGH)
LVTTL output
LVDS non-inverting input
LVDS inverting input
Ground
LVDS inverting input
LVDS non-inverting input
LVTTL output
Enable (active-LOW)
LVTTL output
LVDS non-inverting input
LVDS inverting input
Supply
9397 750 08341
Product data
Rev. 01 — 07 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2 of 16


Part Number PTN3332
Description High speed differential line receiver
Maker NXP Semiconductors
Total Page 16 Pages
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