BLD6G22LS-50 Datasheet PDF (W-CDMA 2110 MHz To 2170 MHz Fully Integrated Doherty Transistor)

BLD6G22LS-50 - W-CDMA 2110 MHz To 2170 MHz Fully Integrated Doherty Transistor

This page provides the datasheet information for the BLD6G22LS-50, a member of the BLD6G22L-50 W-CDMA 2110 MHz To 2170 MHz Fully Integrated Doherty Transistor family.

Description

The BLD6G22L-50 and BLD22LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology.

This device is perfectly suited for CDMA base station applications at frequencies from 2110 MHz to 2170 MHz.

Features

Typical W-CDMA performance at frequencies from 2110 MHz to 2170 MHz: Average output power = 8 W Power gain = 13.3 dB Efficiency = 38 %.
Fully optimized integrated Doherty concept: integrated asymmetrical power splitter at input integrated power combiner peak biasing down to 0 V low junction temperature high efficiency NXP Semiconductors BLD6G22L-50; BLD6G22LS-50 W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor.

Datasheet Details

Part number	BLD6G22LS-50
Manufacturer	NXP Semiconductors
File Size	144.24 KB
Description	W-CDMA 2110 MHz To 2170 MHz Fully Integrated Doherty Transistor
Datasheet	BLD6G22LS-50 Datasheet
Additional preview pages of the BLD6G22LS-50 datasheet.

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Full PDF Text Transcription

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BLD6G22L-50; BLD6G22LS-50 W-CDMA 2110 MHz to 2170 MHz fully integrated Doherty transistor Rev. 01 — 15 December 2009 Objective data sheet 1. Product profile 1.1 General description The BLD6G22L-50 and BLD22LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for CDMA base station applications at frequencies from 2110 MHz to 2170 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only requires the proper input/output match and bias setting as with a normal class-AB transistor. Table 1.

Published: Jan 11, 2010 |