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SI4410DY Datasheet

N-channel TrenchMOS logic level FET

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SI4410DY
N-channel TrenchMOS logic level FET
Rev. 03 — 4 December 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
„ DC motor control
„ DC-to-DC convertors
„ Lithium-ion battery applications
„ Notebook computers
„ Portable equipment
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS drain-source voltage Tj 25 °C; Tj 150 °C
ID drain current
Tamb = 25 °C; pulsed;
see Figure 1 and 3
Ptot total power
dissipation
Tamb = 25 °C; pulsed;
see Figure 2
Dynamic characteristics
QGD
gate-drain charge
VGS = 10 V; ID = 10 A;
VDS = 15 V; Tj = 25 °C;
see Figure 12
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 4.5 V; ID = 5 A;
Tj = 25 °C;
see Figure 10 and 11
VGS = 10 V; ID = 10 A;
Tj = 25 °C;
see Figure 10 and 11
Min Typ Max Unit
- - 30 V
- - 10 A
- - 2.5 W
- 7 - nC
- 15 20 m
- 11 13.5 m


NXP Semiconductors Electronic Components Datasheet

SI4410DY Datasheet

N-channel TrenchMOS logic level FET

No Preview Available !

NXP Semiconductors
SI4410DY
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1S
source
2S
source
3S
source
4G
gate
5D
drain
6D
drain
7D
drain
8D
drain
3. Ordering information
Simplified outline
85
14
SOT96-1 (SO8)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
SI4410DY
SO8
plastic small outline package; 8 leads; body width 3.9 mm
4. Limiting values
Version
SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
VGS
ID
Parameter
drain-source voltage
gate-source voltage
drain current
Conditions
Tj 25 °C; Tj 150 °C
Tamb = 70 °C; pulsed;
see Figure 1
Tamb = 25 °C; pulsed;
see Figure 1 and 3
IDM
peak drain current
tp 10 µs; Tamb = 25 °C; pulsed;
see Figure 3
Ptot total power dissipation Tamb = 70 °C; pulsed;
see Figure 2
Tamb = 25 °C; pulsed;
see Figure 2
Tstg storage temperature
Tj junction temperature
Source-drain diode
IS source current Tamb = 25 °C; pulsed
Min Max Unit
- 30 V
-20 20
V
- 8A
- 10 A
- 50 A
- 1.6 W
- 2.5 W
-55 150 °C
-55 150 °C
- 2.3 A
SI4410DY_3
Product data sheet
Rev. 03 — 4 December 2009
© NXP B.V. 2009. All rights reserved.
2 of 12


Part Number SI4410DY
Description N-channel TrenchMOS logic level FET
Maker NXP
Total Page 12 Pages
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