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NXP Semiconductors Electronic Components Datasheet

PTN3361B Datasheet

HDMI/DVI Level Shifter

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PTN3361B
HDMI/DVI level shifter with dongle detect support and active
DDC buffer
Rev. 02 — 7 October 2009
Product data sheet
1. General description
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The PTN3361B is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the
PTN3361B provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3361B typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or
HDMI v1.3a specification. By using PTN3361B, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure 1.
The PTN3361B main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of DisplayPort
Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. Its I2C-bus control block also provides for optional software HDMI
dongle detect by issuing a predetermined code sequence upon a read command to an
I2C-bus specified address. The PTN3361B also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3361B is a fully featured HDMI as well as DVI level shifter. It is functionally
comparable to PTN3360B but provides additional features supporting HDMI dongle
detection and active DDC buffering. For HDMI dongles, support of HDMI dongle detection
via the DDC channel is mandatory, hence HDMI dongle applications should enable this
feature for correct operation in accordance with DisplayPort interoperability guidelines.
PTN3361B is powered from a single 3.3 V power supply consuming a small amount of
power (90 mW typ.) and is offered in a 48-terminal HVQFN48 package.


NXP Semiconductors Electronic Components Datasheet

PTN3361B Datasheet

HDMI/DVI Level Shifter

No Preview Available !

NXP Semiconductors
PTN3361B
HDMI/DVI level shifter with dongle detect and DDC buffer
MULTI-MODE DISPLAY SOURCE
PCIe PHY ELECTRICAL
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
PCIe
clock
output buffer
pattern TX
FF
TX
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CONFIGURATION
DDC I/O
(I2C-bus)
OE_N
PTN3361B
reconfigurable I/Os
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D4+
IN_D4
OUT_D4+
OUT_D4
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D3+
IN_D3
OUT_D3+
OUT_D3
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2
OUT_D2+
OUT_D2
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1
OUT_D1+
OUT_D1
0 V to 3.3 V
HPD_SOURCE
0 V to 5 V
HPD_SINK
3.3 V
3.3 V
DDC_EN
(0 V to 3.3 V)
5V
3.3 V
SCL_SOURCE
SCL_SINK
5V
SDA_SOURCE SDA_SINK
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1. Typical application system diagram
002aae053
PTN3361B_2
Product data sheet
Rev. 02 — 7 October 2009
© NXP B.V. 2009. All rights reserved.
2 of 29


Part Number PTN3361B
Description HDMI/DVI Level Shifter
Maker NXP
Total Page 29 Pages
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