PHU101NQ03LT Datasheet | NXP Semiconductors

Description N-channel logic level field-effect power transistor in a plastic package using Trench MOS™ technology. Product availability: PHP101NQ03LT in SOT78 (TO-220AB) PHU101NQ03LT in SOT533 (I-PAK). 2. Features s Low gate charge s Low on-state resistance. 3. Applications s Optimized as a control FET in DC to DC converters. 4. Pinning information Table 1: Pinning - SOT78, SOT533 simplified outline and symbol Simplified outline mb Pin Description 1 2 3 mb gate (g) Symbol d drain (d) source (s) mounting base, connected to drain (d) g s MBB076 MBK106 1 Top view MBK915 1 2 3 SOT78 (TO-220AB) SOT533 (I-PAK) Philips Semiconductors PHP/PHU101NQ03LT Trench MOS™ logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 °C ≤ Tj ≤ 175 °C Tmb = 25 °C; VGS = 5 V Tmb = 25 °C Tj = 25 °C; VGS = 10 V; ID = 25 A Tj = 25 °C; VGS = 5 V; ID = 25 A Typ 4.5 5.8 Max 30 75 166 175 5.5 7.0 Unit V A W °C mΩ mΩ drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS VGSM ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 43 A; tp = 0.19 ms; VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V; starting Tj = 25 °C tp ≤ 50 µs; pulsed; duty cycle 25%; Tj ≤ 150 °C Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 175 °C 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ Min - 55 - 55 Max 30 30 ±20 ±25 75 75 240 166 +175 +175...