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NXP Semiconductors Electronic Components Datasheet

PHT1N52S Datasheet

PowerMOS transistor

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Philips Semiconductors
PowerMOS transistor
Objective specification
PHT1N52S
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance.
Intended for use in Compact Fluor-
escent Lights (CFL) and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
520
0.6
1.8
10
UNIT
V
A
W
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
123
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
IDM
IDR
IDRM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
RGS = 20 k
Tsp = 25 ˚C
Tsp = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
WDSR1
Drain-source repetitive
unclamped inductive turn-off
energy
CONDITIONS
ID = 1 A ; VDD 50 V ; VGS = 10 V ;
RGS = 50
Tj = 25˚C prior to surge
Tj = 100˚C prior to surge
ID = 1 A ; VDD 50 V ; VGS = 10 V ;
RGS = 50 ; Tj 150 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MIN.
-
-
-
MAX.
520
520
30
0.6
0.5
2.4
0.6
2.4
1.8
150
150
MAX.
25
10
3.6
UNIT
V
V
V
A
A
A
A
A
W
˚C
˚C
UNIT
mJ
mJ
mJ
1. Pulse width and frequency limited by Tj(max)
February 1998
1
Rev 1.000


NXP Semiconductors Electronic Components Datasheet

PHT1N52S Datasheet

PowerMOS transistor

No Preview Available !

Philips Semiconductors
PowerMOS transistor
Objective specification
PHT1N52S
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-sp
Rth j-a
Thermal resistance junction to
solder point
Thermal resistance junction to
ambient
CONDITIONS
pcb mounted; minimum footprint
pcb mounted; pad area as in fig:2
MIN. TYP. MAX. UNIT
- - 15 K/W
- 156 - K/W
- 70 - K/W
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
VGS(TO)
IDSS
Drain-source breakdown volt-
age
Gate threshold voltage
Drain-source leakage current
IGSS
RDS(ON)
VSD
Gate-source leakage current
Drain-source on-state resis-
tance
Source-drain diode forward
voltage
CONDITIONS
VGS = 0 V; ID = 0.25 mA
VDS = VGS; ID = 0.25 mA
VDS = 500 V; VGS = 0 V; Tj = 25 ˚C
VDS = 400 V; VGS = 0 V; Tj = 125 ˚C
VGS = ±35 V; VDS = 0 V
VGS = 10 V; ID = 1 A
IF = 2 A ;VGS = 0 V
MIN. TYP. MAX. UNIT
520 - - V
2.0 3.0 4.0 V
- 1 100 µA
- 0.1 1.0 mA
- 4 100 nA
- 7.9 10
- 0.85 1.2 V
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
gfs
Ciss
Coss
Crss
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
trr
Qrr
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Total gate charge
Gate to source charge
Gate to drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Source-drain diode Reverse
recovery time
Source-drain diode Reverse
recovery charge
CONDITIONS
VDS = 15 V; ID = 1 A
VGS = 0 V; VDS = 25 V; f = 1 MHz
VGS = 10 V; ID = 2 A; VDS = 400 V
VDD = 30 V; ID = 2 A;
VGS = 10 V; RGS = 50 ;
RGEN = 50
IF = 2 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 100 V
MIN.
0.5
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
0.8
75
10
5
5
.5
3
5
15
15
7
150
MAX.
-
100
15
10
-
-
-
10
20
20
15
-
UNIT
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
ns
1.5 - µC
February 1998
2
Rev 1.000


Part Number PHT1N52S
Description PowerMOS transistor
Maker NXP
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