NXP Semiconductors
PHK31NQ03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information
Type number
Package
Name
Description
PHK31NQ03LT
SO8
plastic small outline package; 8 leads; body width 3.9 mm
4. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage
drain-gate voltage (DC)
gate-source voltage
drain current
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
25 °C ≤ Tj ≤ 150 °C
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
Tsp = 25 °C; VGS = 10 V; see Figure 2 and 3
Tsp = 100 °C; VGS = 10 V; see Figure 2
Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tsp = 25 °C; see Figure 1
IS source current
ISM peak source current
Avalanche ruggedness
Tsp = 25 °C
Tsp = 25 °C; pulsed; tp ≤ 10 µs
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 35 A;
tp = 0.16 ms; VDS ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
Min
-
-
-
-
-
-
-
−55
−55
-
-
-
Version
SOT96-1
Max
30
30
±20
30.4
17.2
121.8
6.9
+150
+150
Unit
V
V
V
A
A
A
W
°C
°C
5.7 A
23.1 A
120 mJ
PHK31NQ03LT_1
Product data sheet
Rev. 01 — 18 December 2006
© NXP B.V. 2006. All rights reserved.
2 of 12
Free Datasheet http://www.datasheet4u.com/
