PHK04P02T
P-channel vertical D-MOS logic level FET
Rev. 02 — 14 December 2010
Product data sheet
1. Product profile
1.1 General description
Logic level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using vertical D-MOS technology. This product is designed and qualified for use
in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for logic level gate drive
sources
Suitable for very low gate drive
sources voltage
1.3 Applications
Battery powered applications
High-speed digital interfaces
1.4 Quick reference data
Table 1.
Symbol
VDS
ID
Quick reference data
Parameter
drain-source voltage
drain current
Conditions
Tj ≥ 25 °C; Tj ≤ 150 °C
Tsp = 25 °C
Ptot total power
dissipation
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
VGS = -2.5 V; ID = -1 A; Tj = 25 °C
VGS = -4.5 V; ID = -1 A; Tj = 25 °C
QGD
gate-drain charge
VGS = -4.5 V; ID = -1 A;
VDS = -10 V; Tj = 25 °C
Min Typ Max Unit
- - -16 V
- - -4.6 A
6
- - 5W
- 117 150 mΩ
- 80 120 mΩ
- 1.83 - nC
Free
Datasheet
