UPA1703 Datasheet | NEC

DESCRIPTION This product is N-Channel MOS Field Effect Transistor designed for power management applications of notebook puters. 8 5 PACKAGE DIMENSIONS (in millimeter) FEATURES - Super Low On-Resistance RDS(on)1 = 10.5 mΩ RDS(on)2 = 17 mΩ - Low Ciss MAX. (VGS = 10 V, ID = 5.0 A) MAX. (VGS = 4 V, ID = 5.0 A) 1 4 5.37 MAX. +0.10 - 0.05 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain Ciss = 2180 p F TYP. 1.44 1.8 MAX. 6.0 ±0.3 4.4 0.8 - Built-in G-S Protection Diode - Small and Surface Mount Package (Power SOP8) 0.05 MIN. 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 - 0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, all terminals are connected) Drain to Source Voltage Gate to Source Voltage Drain Current (DC) Drain Current (pulse) Notes1 Notes2 VDSS VGSS ID(DC) ID(pulse) PT Tch Tstg 30 ±20 ±10 ±40 2.0 150 - 55 to +150 V V A A W °C °C Gate Gate Protection Diode Body Diode Drain Total Power Dissipation (TA = 25 °C) Channel Temperature Storage Temperature Notes 1. 2. Source PW ≤ 10 µs, Duty Cycle ≤ 1 % Mounted on ceramic substrate of 1200 mm2 × 0.7 mm The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device acutally used, an addtional protection circuit is externally required if voltage exceeding the rated voltage may be applied to this device. Document No. D11494EJ1V0DS00 (1st edition) Date Published December 1996 N Printed in Japan © µPA1703...