MPC9100 Datasheet Dual Pll Clock Generator

Manufacturer: Motorola Semiconductor (now NXP Semiconductors)

Overview: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual PLL Clock Generator The MPC9100 is a dual PLL phase locked loop clock generator. The device synthesizes a 14.318 MHz input reference to provide a buffered copy of the input reference, a 31.3344MHz clock output and a 45.1584 clock output.

Datasheet Details

Part number	MPC9100
Manufacturer	Motorola Semiconductor (now NXP Semiconductors)
File Size	114.50 KB
Description	DUAL PLL CLOCK GENERATOR
Datasheet	MPC9100_Motorola.pdf

Key Features

a fully integrated crystal oscillator as the clock reference source. No external components are required other than the 14.318 MHz crystal. The TCLK input is used only for factory test and cannot be used as the PLL clock reference. To reduce total die area the PLL loop filter capacitors are brought outside the chip. The FCAP pins are used to connect these capacitors to the internal PLL’s. 0.01µf capacitors www. DataSheet4U. com are recommended. The device features three synchronous output enable p.

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