MPC9100
features a fully integrated crystal oscillator as the clock reference source. No external ponents are required other than the 14.318 MHz crystal. The TCLK input is used only for factory test and cannot be used as the PLL clock reference. To reduce total die area the PLL loop filter capacitors are brought outside the chip. The FCAP pins are used to connect these capacitors to the internal PLL’s. 0.01µf capacitors .. are remended. The device features three synchronous output enable pins to allow for shutting down specific clocks. When driven to a logic LOW the OE pins will freeze the selected clock in its low state. Internal timing has been established that guarantee transition into and out of the freeze state will not produce output glitches. These control inputs have internal pull up resistors so that they will default to the output active state. The TEST0- 2 pins allow for the testing of the internal logic of the device. Most of the states are reserved for factory test use with one...
