74VHC540 Datasheet | Motorola Semiconductor

features inputs and outputs on opposite sides of the package and two AND- ed active- low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is posed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. - High Speed: t PD = 3.7ns (Typ) at VCC = 5V - Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C - High Noise Immunity: VNIH = VNIL = 28% VCC - Power Down Protection Provided on Inputs - Balanced Propagation Delays - Designed for 2V to 5.5V Operating Range - Low Noise: VOLP = 1.2V (Max) - Pin and Function patible with Other Standard Logic Families - Latchup Performance Exceeds 300m A - ESD Performance: HBM > 2000V; Machine Model > 200V - Chip plexity: 124 FETs or 31 Equivalent Gates DATA INPUTS OUTPUT ENABLES 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 OE1 1 OE2 19 LOGIC DIAGRAM 18 Y1 17 Y2 16 Y3 15 Y4 14 Y5 INVERTING OUTPUTS 13 Y6 12 Y7 11 Y8 MC74VHC540 DW SUFFIX 20- LEAD SOIC PACKAGE CASE 751D- 04 DT SUFFIX 20- LEAD TSSOP PACKAGE CASE 948E- 02 M SUFFIX 20- LEAD SOIC EIAJ PACKAGE CASE 967-...