M2S56D20ATP dram equivalent, 256m double data rate synchronous dram.
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture;
two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.
M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are refe.
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