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M2S56D20ATP-10L, M2S Datasheet - Mitsubishi

M2S56D20ATP-10L 256M Double Data Rate Synchronous DRAM

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input .

M2S56D20ATP-10L Features

* - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat

M2S56D20ATP-10L, M2S Datasheet

This datasheet PDF includes multiple part numbers: M2S56D20ATP-10L, M2S. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number:

M2S56D20ATP-10L, M2S

Manufacturer:

Mitsubishi

File Size:

768.53 KB

Description:

256m double data rate synchronous dram.

This datasheet PDF includes multiple part numbers: M2S56D20ATP-10L, M2S.
Please refer to the document for exact specifications by model.

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M2S56D20ATP-10L M2S 256M Double Data Rate Synchronous DRAM Mitsubishi

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