ZL40260 Datasheet - Microsemi

ZL40260 Low Additive Jitter 2 x10 LVPECL Fanout Buffer

6 Functional Description 8 Clock Inputs 8 Clock Outputs 11 Termination of unused inputs and outputs 13 Power Consumption 13 Power Supply Filtering 13 Power Supplies and Power-up Sequence 13 AC and DC Electrical Characteristics 13 Absolute Maximum Ratings 14 Recommended Operating Conditions 14 D.

ZL40260 Features

* Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML) or single ended LVCMOS signal

* Ten 2.5V/3.3V LVPECL outputs

* Ultra-low additive jitter: 53fs for 125 MHz clock measured in 12KHz to 20MHz band

* Supports clock frequencies from 0 to 1.6GHz

* Supports 2.5V or 3

ZL40260 Datasheet (776.02 KB)