ZL30793
Key Features
- One, Two or Three DPLL Channels
- Packet and/or physical-layer frequency, phase and time synchronization
- Packet-timing pliance with ITU-T G.8261, G.8263, G.8273.2 (class A,B,C&D), G.8273.4
- Enables 5G wireless applications with sub100ns time/phase alignment requirements
- Programmable bandwidth, 0.1mHz to 470Hz
- Hitless reference switching and mode switching
- High-resolution holdover averaging
- Programmable phase slope limit for transients, downto 1 ns/s
- Per-DPLL phase adjustment, 1ps resolution
- Input Clocks
Applications
- Central system timing ICs for SyncE and/or IEEE 1588, SONET/SDH, OTN, wireless base station and other carrier-grade systems
