ZL30256 Description
Block Diagram page 7. Register Map section.
ZL30256 Key Features
- One, Two or Three DPLL Channels
- Programmable bandwidth, 14Hz to 470Hz
- Freerun or holdover on loss of all inputs
- Hitless reference switching
- High-resolution holdover averaging
- Per-DPLL phase adjustment, 1ps resolution
- Programmable tracking range, phase-slope
- Input Clocks
- Accepts up to 10 differential or CMOS inputs
- Any input frequency from 1kHz to 900MHz
ZL30256 Applications
- Jitter attenuation, frequency conversion, and frequency synthesis in a wide variety of system types