ZL30254 Datasheet | Microsemi

Features Input Clocks - Two CMOS inputs, both 8k Hz or 25MHz - Inputs continually monitored for frequency accuracy (±1%) - Automatic revertive reference switching Low-Bandwidth DPLL - 25Hz bandwidth for jitter attenuation - ±120ppm tracking range - Digital hold on loss of all inputs Clock Multiplier APLL and Output Clocks - Easy-to-configure, encapsulated design requires no external VCXO or loop filter ponents - Two CML outputs, both 125MHz or 156.25MHz - Outputs easily interface with CML, LVDS or LVPECL ponents - Output jitter <1ps RMS (12k Hz-20MHz) 2-In, 2-Out 8k Hz/25MHz to 125/156.25MHz Clock Multiplier and Jitter Attenuator Data Sheet April 2016 Ordering Information ZL30254LDG1 ZL30254LDF1 32 Pin QFN Trays 32 Pin QFN Tape and Reel Matte Tin Package size: 5 x 5 mm -40C to +85C General Features - Operates from low-cost 49.152MHz fundamental-mode crystal - Status output pins indicate selected input clock, holdover, and locked/unlocked states - Input clock selection control pin Applications - Jitter attenuation, reference selection from dual 8k Hz or 25MHz inputs, frequency multiplication to 125MHz or 156.25MHz Input...