Datasheet4U Logo Datasheet4U.com

ZL30167 - Dual Clock Translator

Description

17 Precise Frequency Monitor (PFM) 18 Guard Soak Timer (GST) 31 Figure 14 "Typical Power-Up Reset and Configuration Circuit" 32 5.1, “ZL30167 Configuration programming“ 93 Register Name: phasemem_limit_ref0 130 Register Name: dpll0_df_offset 173 13.0, “Package Markings“ Change Included

Features

  • Two independent clock channels.
  • Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs).
  • Four precision synthesizers generate any clockrate from 1 Hz to 750 MHz with low jitter for 10 G PHYs.
  • Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz.
  • Automatic hitless reference switching and digital holdover on reference fail.
  • Nine input references configurable as single ended or differential and two singl.

📥 Download Datasheet

Datasheet preview – ZL30167

Datasheet Details

Part number ZL30167
Manufacturer Microsemi
File Size 690.99 KB
Description Dual Clock Translator
Datasheet download datasheet ZL30167 Datasheet
Additional preview pages of the ZL30167 datasheet.

📁 Similar Datasheet

  • ZL30100 - T1/E1 System Synchronizer (Zarlink Semiconductor Inc)
  • ZL30101 - T1/E1 Stratum 3 System Synchronizer (Zarlink Semiconductor Inc)
  • ZL30102 - T1/E1 Stratum 4/4E Redundant System Clock Synchronizer (Zarlink Semiconductor)
  • ZL30105 - T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer (Zarlink Semiconductor)
  • ZL30106 - SONET/SDH/PDH Network Interface DPLL (Zarlink)
  • ZL30107 - GbE Line Card Synchronizer (Zarlink Semiconductor)
  • ZL30108 - SONET/SDH Network Interface DPLL (Zarlink Semiconductor)
  • ZL30109 - DS1/E1 System Synchronizer (Zarlink Semiconductor)
  • ZL30110 - Telecom Rate Conversion DPLL (Zarlink Semiconductor)
  • ZL30111 - POTS Line Card PLL (Zarlink Semiconductor)
Other Datasheets by Microsemi
  • ZL30160 - Four Channel Universal Clock Translator
  • ZL30161 - Network Synchronization Clock Translator
  • ZL30163 - Network Synchronization Clock Translator
  • ZL30165 - Quad Clock Translator
  • ZL30166 - Triple Channel Network Synchronization Clock Translator
  • ZL30168 - Enhanced Quad Clock Translator
  • ZL30169 - Clock Translator
  • ZL30130 - Stratum 2/3/3E System Synchronizer/SETS

Full PDF Text Transcription

Click to expand full text
ZL30167 Dual Clock Translator Data Sheet Features • Two independent clock channels • Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs) • Four precision synthesizers generate any clockrate from 1 Hz to 750 MHz with low jitter for 10 G PHYs • Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz • Automatic hitless reference switching and digital holdover on reference fail • Nine input references configurable as single ended or differential and two single ended input references • Phase alignment to input 1 Hz frame pulse with associated reference clock (ref/sync pairing) • Any input reference can be fed with sync (frame pulse) or clock • Digital PLLs filter jitter at 5.
Published: |