ZL30166 - Triple Channel Network Synchronization Clock Translator

Product Overview

Microsemi

Datasheet Details

Part number	ZL30166
Manufacturer	Microsemi
File Size	733.66 KB
Description	Triple Channel Network Synchronization Clock Translator
Datasheet	ZL30166 Datasheet
Additional preview pages of the ZL30166 datasheet.

Product details

Description

29 Figure 14 "Typical Power-Up Reset and Configuration Circuit" 30 5.1, “ZL30166 Configuration programming“ 204 13.0, “Package Markings“ Change Included availability of customer defined default configurations Updated GPIO[5:6] power-up settings Updated GPIO[5:6] power-up settings Added section 5.1 Added section 13 for package markings 2 Microsemi Corporation ZL30166 Data Sheet Table of Contents 1.0 Pin Diagram

Features

Three programmable digital PLLs/Numerically Controlled Oscillators (NCOs).
Synchronize to any clock rate from 1 KHz to 750 MHz.
Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with low jitter for 10G PHYs.
Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates.
Digital PLLs filter jitter from 5.2 Hz up to 1 kHz.
Automatic hitless reference switching and digital hol.

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Other Datasheets by Microsemi

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Published: Jan 21, 2024 |